The inventive concept is generally related to semiconductor devices and methods of fabricating same.
Contemporary semiconductor devices are fabricated through a complex sequence of fabrication processes. Some of these processes involve the preparation of substrates, the deposition of materials, the selective etching of material portions, the cleaning of substrates, etc. In the applied aggregate, the complex sequence of semiconductor fabrication processes form very minute structures, components, elements, regions, connections, features, and the like. Emerging semiconductor devices are for the most part even more densely integrated than their predecessors. Thus, the constituent components of contemporary semiconductor devices are designed to be in very close proximity one to another and are generally characterized by incredibly small geometries. Such narrowing proximities and decreasing size necessitate great precision in the application of fabrication processes, as even very small departures from intended design may result in catastrophic failure of the overall semiconductor device.
Nearly all contemporary semiconductor devices include multiple conductive elements arranged at different material layers above a principal substrate. Assigning arbitrary directionality to a semiconductor device, one might say that constituent material layers, and therefore many components and/or regions formed from the material layers extend “laterally” across (or “over”) the primary surface of the substrate. In this context, certain “vertical” electrical connections may be formed between a lower “conductor” (e.g., element or region) and an upper conductor using a structure that will be generically referred to as a via. Hence the term “via” denotes a conductive interconnection extending vertically between two or more conductors disposed at least in part at different “heights” or “levels” (in a Z-direction) above a semiconductor device fabricated on the lateral surface (in X/Y directions) of a substrate.
Recognizing the challenges noted above in the ever decreasing size, scale, geometries and separation distances between semiconductor components, the accurate fabrication of lower conductors, upper conductors, and respective connecting vias are matters of careful consideration and troublesome implementation.
For example, if misalignment occurs between a lower conductor and via, the resulting electrical resistance between the lower conductor and the via may undesirably increase. Further, during the course of via hole formation, an interlayer insulation film provided around a lower conductor may become damaged. Such damage may cause the semiconductor device to operate with reduced reliability.